StackRating
An Elo-based rating system for Stack Overflow
Home
|
About
|
Stats and Analysis
|
Get a Badge
Answers and rating deltas for
Output port missing in generated Verilog code from MyHDL
Author
Votes
Δ
josyb
3
+4.06
Rich Maes
0
-4.06
Last visited: Jun 24, 2017, 4:03:14 PM