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gatecat

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1512.85 (53,421st)

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11 (2,055,902nd)

Page: 1 2

Title	Δ
YOSYS simulating a combinatorial circuit with a specific input	0.00
how to estimation a chip size with standard cell library	0.00
Multiplexer is not simulating changes	-0.10
Executing additional command in Backend that takes the to be genera...	0.00
Is there an option to synthsise some code into verilog built-in pri...	0.00
Path options for techmap calls in a pass	0.00
Using macros for defining bus fields	0.00
Verilog 2's complement adder/subtractor	0.00
Adding cell to write_verilog causes error	0.00
Block Memory on Machxo 2280C always reads Zeros	0.00
Synthesis on yosys	0.00
Is it possible to use $display to print some values when proving wi...	0.00
Addition/Substraction Optimization in Yosys	0.00
Why I can not copy a content of register to another one in "al...	0.00
What are PIP alternative in arachne-pnr?	0.00
Understanding logic tile LC_5 bits	0.00
Yosys ASIC synth flow QoR/PPA metrics	0.00
Trouble getting YOSYS to infer block ram array (rather than using l...	-0.15
Error "does map to unexpanded memory" in yosys verilog wh...	0.00
How to unpack LUTs into logic cells in verilog	0.00
picorv32 risc-v implementation in vivado 2018.2	0.00
MUX in iVerilog: Unable to bind parameter/cannot evaluate genvar ex...	0.00
FSMs extraction with yosys	0.00
Two always block in the same module. If the following technique is...	-4.34
Whether using large arrays such as reg[127:0] temp[0:999] could mak...	0.00
Why the vivado 2017.4 is showing error here?	0.00
Can't create symbole file for module because port has unsupport...	-3.88
Verilog for loop failed to synthesis using oasys	0.00
Constant padding in Verilog	+4.59
Understanding the SB_IO primitive in Lattice ICE40	0.00
Arachne-pnr internal clk reference pin	0.00
RedPitaya hello world hangs up a board	0.00
How to fix Error (10170): Verilog HDL syntax error at <filename&...	0.00
Vivado Clock Implementation error SystemVerilog	0.00
DPI-C and SystemVerilog External Compilation flow issue	+0.54
Signed binary numbers multiplication - chip HDL code	0.00
Is it possible to implement the current Rocket Chip Github respo on...	+3.88
Flash / Run Altera Cyclone IV with OpenOCD	0.00
Is there a difference between always begin vs always blocks?	0.00
Yosys and Synplify compatible elements	0.00
Loading of .hex file in SB_RAM2048x2 ROM and loading of .hex file i...	0.00
what is difference between CLBs MUX based and LUT based	0.00
How to use un-bonded I/O cells in Lattice Diamond Verilog compilers	0.00
Using enum in verilog	+3.90
Is there a verilog coding style checker or formatter?	0.00
Multiple conflicting drivers for reg assigned in only one always bl...	+4.41
Sub-module not found after changing parameter through chparam in a...	+4.00
Mapping of registers to gate level Verilog	0.00
25 MHz clock used for HDMI	0.00
Is there any way to get default parameter value for verilog module...	0.00