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Rating Stats for

FarhadA

Rating
1481.59 (4,490,309th)

Reputation
813 (183,749th)

Page: 1 2

Title	Δ
Using C programming to call VHDL implementation	0.00
Read file in FPGA	-3.83
SPI Between Two FPGAs	0.00
How to debug a C program using SDK on xilinx?	0.00
Transfer data from linux to fpga and inversely?	0.00
Libero soc & ide for windows 7 x32	0.00
Intel De2i-FPGA board PCI	0.00
Spartan 3ADSP device DNA read via JTAG	0.00
Wait until <signal>=1 never true in VHDL simulation	-3.59
EDK Xilinx : File fileset.txt could not be opened in $XILINX direct...	0.00
how to make Xilinx design suite 14.6 EDK work with board ML501 for...	0.00
USB host transfer Android with Spartan 6 FPGA	+4.17
How to vary the supply voltage for Xilinx Virtex-5 FPGA ML501, ML50...	0.00
Read data from FPGA via Android USB	0.00
VGA Text display using VHDL on DE1	+3.69
Conditional UCF statements or conditional UCF file inclusion	+4.18
How to take samples using fpga?	-3.27
how to connect nexys2 FPGA with camera? Driver issue	0.00
Connecting multiple usb peripherals to a FPGA	0.00
In VHDL ..... how to count leading zeros of vector?	+0.61
Verilog accessing memory address	+0.34
Generating Single Port ROM on Spartan 6 using Xilinx ISE Design Suite	-0.95
Displaying Two Different Variables On The 7 segment LED Display wit...	+0.22
What are examples of FPGA or ASIC clusters outside of Bitcoin?	-3.73
How can my vhdl code and microblaze co-exist?	0.00
Sasebo GII virtex5 fpga configuration	0.00
Listen for GSM traffic	-3.83
Struggling with waiting for transfer completion with VHDL	-1.65
LOC constraint value	0.00
Synthesis and Simulation Independent Clock Divider	-1.78
GNURADIO: Getting stream tags to pass over more than one block?	0.00
PCI/PCIe card with DMA capability for device driver training	0.00
Graph/schematic generator for VHDL	-3.99
how are process'es evaluated in practice	+0.18
Can I send a signal with a certain frequency and data rate using my...	+0.09
Verilog code . Help Needed on always statement	-4.04
Verilog always block	0.00
How to send a video file with GNURadio and USRP's?	-0.09
Linux can not detect Altera FPGA	0.00
Debugging Iteration Limit error in VHDL Modelsim	0.00
How can I calculate propagation delay through series of combination...	-1.15
Xilinx Virtex5 Simple I/O	0.00
Sampling Frequency for capturing the wlan signal in USRP2	0.00
USRP2 FPGA debugging	0.00
gnuradio build error	0.00
Xilinx ISE fails to use std_logic_1164	0.00
How to setup USRP2	0.00
Datatype problem in simple IF statement in VHDL	0.00
I can't open project I closed in Quatrus in windows 7	0.00
decoding 802.11 b	0.00