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Rating Stats for

Charles Steinkuehler

Rating
1494.88 (4,278,360th)

Reputation
2,965 (57,037th)

Page: 1 2

Title	Δ
Can't infer register in Quartus II (VHDL)	0.00
Can't compare = in VHDL with std_logic_vector types	0.00
Configuration of LCD: sending and transmission timing	-0.01
Undefined output of Ring Counter Test waveform	+4.37
Define a method for record in vhdl	+0.64
When do signals get assigned in VHDL?	+0.67
Use of concatenation to shift in VHDL	0.00
convert integer to std_logic	+2.62
necessity of 'event	-3.54
Sharing (including?) generics in VHDL between files?	+4.72
Problem in VHDL std_logic_vector place values	+0.48
Shift Right And Shift Left (SLL/SRL)	-1.40
Creating a frequency divider in VHDL	-3.50
My counter "4-digit BCD Counter" does not work well!	-4.00
Where to declare a constant or type used in an entity declaration?	+4.67
Tristate buffers in Quartus II	-3.93
Use a generic to determine (de)mux size in VHDL?	-1.53
How to assign pins in Quartus II	0.00
VHDL group multiple std_logic_vectors output into a single std_logi...	0.00
VHDL syntax for arrays of clocks (accepted by synthesis but not Act...	+4.63
Purpose to providing more than one architecture?	-1.75
Array Type mismatch in VHDL	0.00
Equivalent of #ifdef in VHDL for simulation/synthesis separation?	-3.86
Ideas for a flexible/generic decoder in VHDL	-3.95
Subprocedure call in VHDL	-3.88
Portmapping a vector to a std_in in VHDL?	0.00
SRA can not have such operands?	-3.71
How can I write a simple pseudo assembler?	+4.00
adding '1' to LOGIC_VECTOR in VHDL	-3.92
Reading OUT ports for debugging	-0.11
Problem with net instantiation	+4.10
Making a 4-bit ALU from several 1-bit ALUs	-4.02
"Serialize" VHDL record	-4.12
VHDL Case/When: multiple cases, single clause	0.00
VHDL components	+4.29
Load half word and load byte in a single cycle datapath	0.00
Why IEEE vhdl standard library is not STL?	+3.91