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simon

Rating
1498.34 (3,859,697th)

Reputation
870 (173,708th)

Page: 1

Title	Δ
add_dependencies transitivity with add_subdirectory	0.00
VHDL Counter circuit error	0.00
Why it is necessary to use internal signal for process?	-0.38
This is the code for a serial adder of 6 bit numbers in VHDL.There...	+3.88
How to use components inside behavioral vhdl	+0.02
XOR using a 4:1 Mux in VHDL	+0.09
VHDL initialize vector (the length is not a multiple of 4) in hex	-1.31
VHDL - Why is this signal never driven low?	0.00
VHDL - Dynamic std_logic_vector size	0.00
VHDL bit aggregation	-0.02
Synthesis and Simulation Independent Clock Divider	-1.90
how are process'es evaluated in practice	+4.20
Error compiling kernel module for simple device driver	-2.87
Segfault while copying string	+4.05
Open a file in Eclipse	-0.24
FIFO control signals and extraction of bits for routing logic	0.00
What is this VHDL code setting max and min to? An explanation of fi...	0.00
Can I have conditional constants in VHDL?	-3.51
Concatenation of the same bits	+0.02
LCM of two 5-bit numbers	0.00
vhdl ram module and use of registers	-3.72
Is there a better way to re-write a BCD_counter in VHDL code with l...	+2.30
Behavior of VHDL comparison operator with integer argument	-1.88
why is the following not writing array content to file	-0.39