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Rating Stats for

Kevin Thibedeau

Rating
1525.72 (23,052nd)

Reputation
2,732 (61,845th)

Page: 1 2 3

Title	Δ
What is the iteration error in the loop?	-0.13
How can I make Modelsim warn me about 'X' signal?	0.00
capture vsim exit code or current simulator state with script	0.00
calculate logarithm using VHDL	0.00
list() function won't separate string into characters	-0.89
vhdl - incrementing a vector in the complex plane by a fractional a...	0.00
multiple assignment of concurrent statement	0.00
Strange spikes in the signal ModelSim VHDL	0.00
Reading file, outputting UTF-8/Unicode	+0.05
State Machine with VHDL for UA(R)T	0.00
How do I get the original characters with python?	-2.10
Python: pip installing requests for older version: 2.7	0.00
Migration from distribute to setuptools	0.00
What should I install Distribute or Setuptools	0.00
A simple VHDL circuit won't display initial value	-3.59
No default binding for component instance "d0 : or2". # (...	0.00
Function Syntax not compiling - VHDL	+0.09
How to send some data 10 times with a delay of 10 ms between chunks...	0.00
Creating a generic multiplexer	+4.47
Slice component allocation for carry multiplexer	0.00
Adding Even Parity bit and 2 stop bits to a 8 bits std_logic_vector	-4.07
How to drive a clock to a single clock domain?	0.00
VHDL unconstrained array of unconstrained array	0.00
How to allow two processes to change the value of the same signal	0.00
Clock divider simulation	-3.32
Adding Library to VHDL Project	-0.05
how to use 8 bits from 32 bit array of unsigned/signed bits	+0.06
Keypad encoder why with 8 states?	0.00
ethernet port Pin constraint for Zedboard (phy0_dv pin ??)	0.00
how to split brackets using python abcd[00451.00]	-1.17
matrix enlargement in vhdl	0.00
Generic bitslip module	0.00
One Random.Randint to assign diff numbers to multiple varibles / st...	-0.62
VHDL - using two components in a third entity	0.00
How to learn to write VHDL test benches?	+3.54
VHDL- vector slicing	+1.70
Why is my VHDL detector not recognizing the state change?	0.00
Inferred RAM doesn't initialize in ModelSim Altera edition	+0.13
setup.py packages and unicode_literals	-3.37
read README in setup.py	0.00
python for loop to find and print names from blizzard api behaving...	+3.90
How to write input values at different clock cycles in test bench o...	-0.05
Split variable line by line python	+0.31
Symmetric Cipher HDL	-3.96
HOWTO debug pythion logging config file errors	+3.96
Standard ASCII File Format For Plotting from Matplotlib	-2.12
I need to multiply 2 numbers in tuples	+2.72
pseudorandom pattern generator, output is not changing	0.00
Fused AND gate in VHDL	0.00
Difference between MMU and memory controller	0.00