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Rating Stats for

chitranna

Rating
1485.19 (4,469,299th)

Reputation
916 (166,441st)

Page: 1

Title	Δ
Creating pulses of different width	+0.74
How do I make modules run sequentially?	+0.15
What happens when using concatenation operator {} this way	-3.77
Difference between 'wait' and '@' statement	0.00
Verilog blocking and non-blocking in a sequence	0.00
Reg not incrementing in synchronous always block	0.00
Continuous assignment verilog	-3.74
Non Blocking or Blocking assignment for a buffer?	-3.97
Verilog why is [NumberOfBits-1:0] and what is it actually doing	-3.16
How does a simple state machine look in Verilog?	+0.86
2D Arrays in Verilog	0.00
Verilog : Use of assign and always	0.00
Colors and Styles in Android	-1.92