StackRating

An Elo-based rating system for Stack Overflow

Home | About | Stats and Analysis | Get a Badge

Rating Stats for

JCLL

Rating
1479.29 (4,499,417th)

Reputation
2,692 (62,763rd)

Page: 1

Title	Δ
ghdl-yosys-plugin compilation failed	0.00
Ruby Gtk3 memory leaks using Cairo	+4.21
IEEE from Synopsys in GHDL : passed as option, but not correctly ta...	+1.28
Wait Statement error in VHDL	0.00
View graphml file	0.00
Translating a Java internal class into a JRuby counterpart	+0.42
No feasible entries for infix operator "-"	0.00
Treetop seems to fail on a simple grammar (5 rules)	0.00
VHDL- vector slicing	+2.28
Extract number + letter combination from string	-3.24
Formatting mathematical functions	0.00
How to flash a bitstream file in a PROM on Digilent Xilinx FPGA boa...	0.00
efficient integration of FPGA into computer system	-2.52
Java array beginner confusion	-3.89
How does adding a caret to the start of square brackets affect the...	-0.39
How to Rewrite FSM not to use Latches	-1.58
VHDL types mismatch during simulation MODELSIM	0.00
VHDL strange behaviour	0.00
Where is Ruby code compiled when using javascript HotRuby.js?	0.00
ruby - require & cannot load such file	-3.84
Ruby StringScanner used for lexing : how to get the line number?	-0.34
Is this a Ghdl/gtkwave bug?	0.00
How do languages related to FPGAs?	+0.52
Generating and importing basic drawings into Inkscape?	0.00
Implementing a real-time, run-time compiler on an FPGA	-1.16
Embedded Linux and device driver development	-0.80
Is there a more ruby-esque way to do this?	-3.72
Where to force xilinx ISE to use block-rams?	-3.95
example extending LEON SOC with custom peripheral, AMBA AHB slave	0.00
Creating a VHDL backend for LLVM?	0.00
'if' vs 'when' for making multiplexer	-3.98
fpga: choosing c++ to program fpga	0.00
Graph drawing for the Web 2.0	0.00
Dataflow Programming Languages	0.00