StackRating

An Elo-based rating system for Stack Overflow

Home | About | Stats and Analysis | Get a Badge

Rating Stats for

nguthrie

Rating
1493.93 (4,312,491st)

Reputation
1,718 (96,333rd)

Page: 1

Title	Δ
What are the difference in delay times of the basic AND, OR, NOT, N...	+0.26
any way how to define msb:lsb range as parameter?	-2.89
Is there a way to switch a register from positive to negative of th...	0.00
Verilog: always@* block not getting triggered	+1.30
How to synthesize hardware for SRA instruction	+4.06
Parameterizing an incomplete case statement in Verilog	0.00
Verilog : Is there an idiom for an incrementing compile-time counter	-0.02
Verilog part select in a genvar context	+4.15
In Verilog, how do I use a variable in logic	0.00
A yellow icon appears at toggle of signal in ncsim. Cant make out w...	0.00
Rounding off with zero at the end	+0.15
Passing unpacked array type as parameter	-1.95
creating a 4Kb Data structure in systemverilog	-4.26
SystemVerilog 'if' statement inside always_comb 'not pu...	+4.51
How do you join several input wires into one wire in systemverilog...	+0.42
Chisel adding enable to a register that has a next field	-3.96
Modify verilog mode indentation	0.00
About the latches generated by "case" syntax	+4.28
Others => '1' statement in Verilog	+0.05
How to use verilog $deposit with indexes	0.00
Width independent functions	+4.20
How to implement a special selector	+0.19
Verilog possible latch	+4.23
Verilog instantiate issue?	0.00
Solving endless loop in verilog	0.00
using assign statement for `define statement	+4.29
What does #1 mean in verilog?	-3.61
Constraints for arrays in system verilog	-3.55
Complex port connection in Verilog	0.00
Binary to Gray Conversion	-3.73
passing a class as data between synthesized and unsynthesized modul...	-3.73
How does a system verilog structure be realized in hardware? are th...	-3.82
What is parasitic state machine in Johnson counter	0.00
Verilog: Input Signal as Parameter	+2.15
Does UVM support nested/inner classes?	-3.88
Verilog: Passing parameters	-3.11
How to set all the bits to be 0 in a two-dimensional array in Veril...	-1.71
change verilog 16x4 unidirectional mux to bidirectional mux	0.00
Assigning entire array in verilog	-3.94
How to read an FPGA implementation report	0.00
Difference between scoreboard and checker	-4.16
Verilog Register to output	-0.03
How to parameter MUX using SystemVerilog	+3.90
Best way to access the uvm_config_db from the testbench?	+4.00
How can I use foreach and fork together to do something in parallel?	+0.13
Rounding floating point numbers in Verilog?	0.00
How to implement a (pseudo) hardware random number generator	0.00
How to avoid very last assertion (if I understood it properly)	0.00
Using Regular Expressions for Verilog Port Mapping	0.00