StackRating

An Elo-based rating system for Stack Overflow

Home | About | Stats and Analysis | Get a Badge

Rating Stats for

SDGator

Rating
1488.71 (4,434,355th)

Reputation
1,260 (127,085th)

Page: 1

Title	Δ
Wait for set of qsub jobs to complete	0.00
Does anybody have quantitative data on VHDL versus Verilog use?	0.00
Building a Regex Composer	+3.14
Signals and Variables in VHDL (order) - Problem	-1.68
Configuration Management for FPGA Designs	-0.41
Algorithms FPGAs dominate CPUs on	-1.15
Search and replace hundreds of strings in tens of thousands of files?	+1.54
The best distribution of cameras inside a room	-1.79
I'm going to be teaching a few developers regular expressions - wha...	0.00
Why byte b = (byte) 0xFF is equals to integer -1?	-3.18
What's a quick way to comment/uncomment lines in Vim?	-2.70
Regexp match any uppercase characters except a particular string	-1.19
How to detect EOF in awk?	+4.23
Joomla 1.5 add next link or image to article	0.00
Efficient way to compare two strings (ordering of characters irrele...	-2.44
Why is number of bits always(?) a power of two?	+1.67
Notify upon any serious errors on logs	0.00
Beginner: Do I have to use templates when implementing my own desig...	-1.80
VHDL How to add a std_logic_vector with a std_logic signal together?	-2.61
Design of an Alternative (Fluent?) Interface for Regular Expressions	+1.13
Show/Hide (drop/down) area to show a menu	+0.02
Joomla from scratch	-4.07
Capcha Community Builder	0.00
Mastering Joomla	+4.01
finding all dependencies in a verilog compile	-4.02
Why my filter output is not accurate?	0.00
Exporting tasks to 'C using DPI	0.00
verilog or systemc for testbench	0.00
Is there a Perl tutorial for Verilog engineers?	0.00