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toolic

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1621.40 (1,065th)

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35,458 (3,239th)

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Title	Δ
Requesting and Gathering Names for (x) number of people?	0.00
Can't print the size of a hash of hashes or access element within i...	-0.66
Function Reuse in Verilog	0.00
Perl array splicing syntax	+2.54
Use of forever and always statements	-0.49
My Verilog behavioral code getting simulated properly but not worki...	+1.21
What is the reason to use parenthesis-less subroutine calls in Perl?	-0.00
Verilog sequence of non blocking assignments	+0.13
parallel execution of module under always block	0.00
What is the difference between structural Verilog and behavioural V...	0.00
Issue with Logic in Verilog	-1.80
Can I use $urandom_range with time variables	0.00
How to zero-extend a number if it is valid, or X-extend it otherwise?	-0.52
CPLD Pins not being driven	+1.10
Cannot find why value doesn't jump to expectation in the right time	0.00
Error In Finding Number of Elements In Array (Perl)?	-1.17
how to nullify register in system verilog	+1.33
Unusual function declaration in Verilog	0.00
Simple CPU design in Verilog	0.00
Are there compiler directives for specifying the type of adder synt...	-1.81
What to do when a latch cannot be avoided?	+0.89
error on verilog instance?	-0.56
Counter With Frequency divider is not incrementing	-0.56
Illegal reference to net error	0.00
Calculating in input	+0.23
My code does not move onto the next state even when the conditions...	0.00
Ripple Counter Using Dflip flop	-0.57
Data is not picked up from instantiated outputs	0.00
Verilog: connect modules port without instantiating a new wire	-0.05
How to create an executable PrimeTime script?	0.00
Verilog calling a multiplexer module in another module	0.00
Instantiation of a module in verilog	-0.08
Verilog: Mix of blocking and non-blocking assignments to variable &...	0.00
Copy XML value using XML twig perl	+0.23
How to convert a string number to a real number?	+2.11
Half Tone pixel converter output is undefined	0.00
Perl Regex Filename Not Matching	+0.03
Passing a hexadecimal value into a module in Verilog	+0.48
How to make Perl's Devel::Cover ignore certain lines in coverage to...	-0.38
Assert statement in Verilog	+0.45
Hexadecimal to BCD Conversion	+0.45
Verilog simulation gives x as output	-0.56
Initialization of array error in Verilog	-0.53
Convert VHDL code to Verilog	-0.59
Can I give part selects meaningful names in verilog?	-0.04
What does the cat command in quotes in a string in perl do?	-1.65
A module to generate a table automatically in perl	-1.23
Using static values in Verilog	0.00
Perl regular expressions	-0.08
When are `include directives not needed in Verilog and SystemVerilog?	-0.71