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Rating Stats for

Peter Cordes

Rating
1575.42 (3,453rd)

Reputation
156,434 (349th)

Page: 1 2 3 4 ... 92

Title	Δ
How to test performance of Intel HyperThreading in Linux X86_64	0.00
How memory aligment and access granularity work in assembly?	0.00
Time required to access the memory locations in the same cache line	0.00
TLS Data Address the Same in All Threads	0.00
why could some instructions be excuted in one clock cycle in modern...	0.00
Is it possible to use the same register as a memory pointer and dat...	0.00
Two's complement representation of numbers	0.00
Where is the architecture support implemented in GCC, clang, and/or...	-1.21
Generated Assembly For Pointer Arithmetic	+2.14
Why is this jump instruction so expensive when performing pointer c...	0.00
Fastest way to calculate the Hamming distance between 2 binary vect...	0.00
In the Harvard Architecture, are there two MAR's and MBR/MDR...	0.00
Tracing and disassembling Linux Kernel instructions not matching ke...	0.00
Is cycle count itself reliable on program timing?	0.00
Cache miss latency in clock cycles	0.00
Behavior of breakpoint on relaxed memory models	0.00
Does memory copying on APUs (e.g. apple m1 mac) use GPU-specific wi...	0.00
How to read this line with three(?) operands?	0.00
x86 SIMD instructions 16 byte alignment in assembly (Without C intr...	0.00
Set on Less Than Immediate Unsigned: Range of representable integer...	0.00
Long long in c99	-0.89
How do I synchronize a store before a load in multiple threads?	0.00
Have compiler ignoring setting an argument register before calling...	+0.21
Expand the lower two 32-bit floats of an xmm register to the whole...	0.00
Difference between assembly and disassembly in XCode	0.00
In buffer overflow, how new return address aligns perfectly?	0.00
Need Interpretation of 64bit Assembly Instruction As Opposed to 32bit	0.00
will work out how far apart two letters are in the alphabet	-0.84
Do gcc vector extensions support variable length vectors?	0.00
Why are there no NAND, NOR and XNOR instructions in X86?	0.00
What is an alternative way to see length of a string in ASM?	-0.61
How does write-invalidate policy work with set-associative caches?	0.00
Analog of _mm256_cmp_epi32_mask for AVX2	0.00
Why gcc generates a PLT when it is apparently not needed?	0.00
Reasons a C Compiler Ignores register Declaration	0.00
Will the IDE disk controller's register confuse when read and w...	-2.74
Does a Length-Changing Prefix (LCP) incur a stall on a simple x86_6...	0.00
What is faster in C++: mod (%) or another counter?	+0.39
Why is this assembly program crashing (re-assembled ndisasm output)?	0.00
How to access segment register with out linking libc.so?	0.00
NASM - Storing the address of one variable in another variable	+0.38
c++ lock free queue implementation single producer single consumer	+1.70
Why do my results different following along the tiny asm example?	0.00
Inline assembly statements in C code and extended ASM for ARM Corte...	0.00
Why does a write system call print a bunch of junk when you mov edx...	0.00
Is clflush or clflushopt atomic when system crash？	-1.40
Why would I use NASM over GNU Assembler (GAS)?	0.00
How to preserve an array or string in x86	0.00
What data will be cached?	+1.63
How do processors know the order of registers' values?	+1.31