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Rating Stats for

Peter Cordes

Rating
1575.42 (3,453rd) 		Reputation
156,434 (349th)
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Title Δ
Counting bits in arm assembly 0.00
What's the proper way to recurse in LLVM assembly? +0.16
os x 32-bit printf from assembler 0.00
Intel 64 bits, strange RSP behavior 0.00
Inline assembly with argument reorders code -2.18
Find 4 minimal values in 4 __m256d registers +2.76
What's the relation between hexdump and asm? 0.00
Refactor part of a program to a loop to make it smaller 0.00
How to access a char array and change lower case letters to upper c... -0.47
MASM Mov from/to immediate memory address -0.00
How does CLFLUSH work for an address that is not in cache yet? -1.32
De-interleave image channel in SSE 16 bit vectors 0.00
Handling zeroes in _mm256_rsqrt_ps() 0.00
Why aren't those function calls optimized? -1.22
Get argv[2] address in assembler x64 0.00
Why are some Haswell AVX latencies advertised by Intel as 3x slower... 0.00
Will Speculative Execution Follow Into an Expensive Operation? 0.00
How come the following x86_64 assembly gives me a segmentation fault? 0.00
Lookup table vs switch in C embedded software -0.43
RethinkDB for i586 -0.51
Can x86 reorder a narrow store with a wider load that fully contain... +0.49
Using ".init_array" section of ELF file 0.00
Can VEX prefixes be used with general-purpose instructions? 0.00
Faking ASM Return Address? -2.59
Intel broadwell uop fusion for AVX load/store instructions 0.00
It's possible to programmatically list all the registers on an... -0.51
Is the flag -ffixed-<reg> always bugged in GCC? +0.48
nasm: Is "global _start:" allowed? 0.00
_mm_testc_ps and _mm_testc_pd vs _mm_testc_si128 0.00
Faster lookup tables using AVX2 0.00
Atomic int64_t on ARM Cortex M3 -1.65
clflush implementation: Why's m8 in "Flushes cache line co... 0.00
Assembly Language - What is the register of an temp string input -0.04
Masm assembly 8086 carry flag between data word addition -0.47
Linux difference between when to use parentheses -0.51
MOVAPS accesses unaligned address 0.00
Sqrt in Assembly x86 0.00
Why is the loop instruction slow? Couldn't Intel have implement... 0.00
Assembly Language Loop Not working +0.46
Encoding DNA strand in Binary +0.44
Optimisation using SSE Intrinsics 0.00
Efficient bit shuffling between multiple words -0.54
How to use SSE Intrinsics to subtract two different parts of the sa... 0.00
per clock perf. - can I use different registers for same instruction? 0.00
Can I make C++ generate cmpps instruction without inline assembly? +2.07
Retrieving values through address in assembly 0.00
Intel FMA Instructions Offer Zero Performance Advantage -1.84
replace _mm_cvtepi16_epi32 using only SSE3 0.00
Behavior of stack addressing and esp usage 0.00
How to speed up my memory scan program? -2.03