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Rating Stats for

OllieB

Rating
1491.54 (4,390,085th)

Reputation
1,040 (149,868th)

Page: 1

Title	Δ
What happens when I delete a pointer of pointer?	-1.20
Bidirectional Arrow	-3.17
Can I call functions inside PORT MAPs?	0.00
Performance of iterator list comprehension	+4.44
Simulating interacting stateful objects in Haskell	-2.07
Discoverability of Functional Languages' Functions	-3.27
Is there a more natural way to represent a matrix of T than a vecto...	+1.60
Can I use data types like bool to compress data while improving rea...	-1.49
Shifting more than 8 bits - leading to wrong output	-0.82
VHDL - same bitstream, two boards -> inout issue	+0.59
VHDL with select when error	0.00
vhdl asynchronous assignment in for loop	-2.58
Generating documentation for mixed VHDL/Verilog projects	0.00
How do I go about writing a parser?	-3.95
C++ loading Matrix from file and Construct	-0.04
Refactor if-else-if structure	+0.94
Set and reset on rising and falling edge	+4.01
Set and reset on rising and falling edge	+0.01
Driving GPIO pins shared with SRAM in VHDL	-0.08
Lua - If and and, what is faster?	-3.57
Rotating an image based on different coordinat systems	+3.94
Using C++-AMP to reduce runtime of unsorted vector search	0.00
Canot compute minmal length of a parser - uu-parsinglib in Haskell	-3.82
Monadic parse with uu-parsinglib	-4.12
Assignment to part of a multi-dimentional array in VHDL	0.00
QuickCheck test randomly hangs	-3.89
DCF77 decoder vs. noisy signal	+4.07
uu-parsinglib parsing with conditional fail	0.00
32 Bit ALU in VHDL Carry Out	+4.54
Handling Interrupt in VHDL	+0.68
Asynchronous asymmmetric FIFO in VHDL synthesis issue	-4.00
VHDL - Conditionnal attribute declaration depending on a generic	+1.72
Adressing a specific bits in an array of std_logic vector in VHDL	0.00
Cannot Synthesize Signal	0.00
Why can't I synthesize this VHDL program?	-1.75
VHDL clock divide in decimal	+0.31
Source Code via "Hyperlink" for Documentation	0.00
Business Role that Manages Technical Documentation	0.00
cyclically 8 bit shifter ,VHDL	-0.18
VHDL synthesis of registers - separate process for each register vs...	+4.68
ultra low power adders and multpliers vhdl	0.00