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Jamey Hicks

Rating
1497.61 (3,943,298th)

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1,782 (93,147th)

Page: 1 2

Title	Δ
/dev/mem or user space burst transfer; how to get faster /dev/mem a...	0.00
mmap, axi and multiple reads from pcie	0.00
How can I program FPGA from ANDROID DEVICE? Give me an idea, please	+4.06
What is the memory map section in RISCV	0.00
FPGA IO configuration: Effect of weak pull up/down on an output	0.00
Alternative to the GPL find_symbol method in Linux kernel module	0.00
Does the Linux kernel project use some build automation software to...	0.00
Use Vivado tool with create_clock and create_generate_clock	+0.08
Write to a UIO Device	0.00
Using memcpy on mmap'ed region crashes, a for loop does not	0.00
does FPGA reset automatically after programmed?	0.00
The need of Xilnx AXI BRAM Controller IP	+4.12
SD card protocol over Ethernet	+0.06
When I cross data from a slow clock to a fast clock domain, wouldn&...	0.00
How to use LogiCORE DSP48 Macro?	0.00
Can multiple drivers register to handle same device in linux	0.00
Ethernet connection from FPGA to PC	0.00
Kernel to user space communication with low latency	-3.26
Detailed timing information of how much latency each sub-component...	+4.33
How to merge synthesis results in Vivado	0.00
Bitwise operations with Floats Python	0.00
External xilinx PCie driver with Yocto	0.00
git checkout -f in python	+4.25
I2c Master testing on FPGA board	0.00
PCIe DMA Driver for Linux	-3.54
Linux PCIe DMA Driver (Xilinx XDMA)	-0.07
Compiling kernel from source. error explaination.	0.00
FPGA - CPU Latency measurement with C/C++	-2.65
Linux device driver maps serial fpga registers to memory	0.00
Why did PCI Express suffer high latency in pipeline transfer mode?	0.00
Android kernel run fanotify without rooting?	0.00
Do Compilers for FPGA Languages Perform Optimizations?	-3.21
How to put files into riscv linux?	0.00
Calling python from matlab - SSL module is not available on Ubuntu...	0.00
DMA transaction requires copying into buffer every time?	0.00
Enable hardware SPI on Xillinux	-0.03
Spike: error while loading shared libraries: libriscv.so	0.00
Cross compile module with arm-eabi-gcc	-2.04
RISCV and Spike: Add something and read value	0.00
is there a way to run network(socket) program in RISC-V?	0.00
Debug Linux kernel in a board without GDB	0.00
Is it possible to do interactive user input and output simulation i...	-2.83
Vivado version difference first stage boot loader	0.00
Kernel Panic in a linux kernel image that is running on a xilinx FPGA	0.00
Kernel driver - ZedBoard - Linux hangs after accessing address	0.00
What is practical way for GUI control for FPGA logic?	0.00
Connecting Zynq boards in deterministic way	0.00
xilinx xps using command line mode	0.00
Need help mapping pre-reserved cacheable DMA buffer on Xilinx/A...	-4.03
Why wont Xilinx ISE accept this statement in a state machine?	0.00