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Rating Stats for

Khanh N. Dang

Rating
1500.71 (431,596th)

Reputation
641 (223,449th)

Page: 1

Title	Δ
Width mismatch vhdl at constant declaration	-4.05
How to infer block RAM in Verilog	0.00
Connecting multidimensional systemverilog port to vhdl module	0.00
VHDL 4 Bit Comperator using 2 Bit Comperator	0.00
VHDL std_logic_vector indexing with "downto"	+4.30
How do you enable a graphical interface for the Red Hat Enterprise...	-4.05
"unsigned" type conversion demands input in sequential pr...	-3.82
VHDL - Successive Approximation Register	+0.18
Verilog Error: Can't elaborate user hierarchy "counter:counter...	0.00
Designing a Combinational Shift Operator in VHDL	+4.24
VHDL - Need some advice on division & multiplication	0.00
Signals and Variables in VHDL	-0.00
VHDL: use the length of an integer generic to determine number of s...	+4.10
VHDL Counter result giving X	+4.14
conv_integer in vhdl	-4.33
warning message at the prompt	0.00
Why does Modelsim 10 not compile older code?	0.00
VHDL: how to set a value on an inout port?	0.00