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Rating Stats for

Morten Zilmer

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1580.34 (2,977th) 		Reputation
12,768 (11,398th)
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Lightweight VHDL simulator in Windows +0.25
Ring Oscillator 0.00
vhdl assign specific bit of std_logic_vector with index failed 0.00
How can I extract elements from a record using an integer reference... -0.32
vhdl programming scale the value from 32 scale to 100 scale -2.38
vhdl convert subtype to type for active hdl 0.00
VHDL : writing an AND function -1.99
Is there a way to use one testbench for different simulators if bot... +0.40
Errore VHDL Quartus +1.03
Error (10822): couldn't implement registers for assignments on... 0.00
fatal error in modelsim during simulation -0.33
Is there a way to print the values of a signal to a file from a mod... +1.04
Entries for Subprograms in VHDL 0.00
Array Type is not constrained - VHDL 0.00
VHDL- use of variables 0.00
Force VHDL to use generic over constant 0.00
Assign two signals from the same statement -0.46
Divide negative number in VHDL by shifting 0.00
Do I have to write the `else` statement when implementing a registe... +2.03
Std_logic_vector adding function -0.32
Split n long bit logic vector to n individual binary values 0.00
LIFO memory vhdl code understanding 0.00
4bit ALU VHDL code -0.46
Structure of VHDL code for barrel shifter with behavior architecture +0.41
modulo n generic counter 0.00
Convert 8bit binary number to BCD in VHDL -0.32
VHDL problems with parity check 0.00
A simple VHDL circuit won't display initial value +0.04
LFSR in VHDL always generating zero 0.00
VHDL nested case statement for some case options -0.39
Creating a generic multiplexer -1.47
wait on an untimed signal in VHDL testbench +0.74
Why the clk_divider not working? 0.00
Implementing an OR gate with for-generate 0.00
How to resolve this coding error +2.24
How to add std_logic to an integer value 0.00
UART RS-232 Transmitter -2.00
Unexpected delays with register VHDL +1.68
VHDL simple optimization 0.00
Specify matrix row error +0.40
Clock divider simulation +0.41
Synchronous Counter Issue -0.31
Testbench in VHDL -0.11
Assign signal in two processes in VHDL -1.68
how to split 16 bit data into 2 8-bit data. VHDl +0.82
Understanding a simple VHDL process 0.00
python 3 select just the integer from a list with strings -0.21
Generate ports in VHDL? 0.00
VHDL unsigned vector vs integer comparison 0.00
How to connect output port to input port 0.00