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Rating Stats for

Vasiliy

Rating
1554.91 (6,655th) 		Reputation
9,659 (15,868th)
Page: 1 2 3 4
Title Δ
Do I need to close a Cursor if moveToFirst() is false? +3.96
Asynctaskloader restart loading when the activity restart 0.00
Can not perform this action after onSaveInstanceState 0.00
How to pass same String value from adapter to two different activit... 0.00
Is cyclic dependency between anonymous class and parent class wrong? -0.22
Same CursorLoader by extending activity 0.00
Android: Tabbed activity with bluetooth and graph plotting, how to? 0.00
TextView in thread error -2.72
Splitting big classes with Inner classes in Java +3.97
ListFragment appearing twice on phone -4.02
getArguments throws NullPointerException +4.05
How do implicit joined columns work with Android contacts data? 0.00
Scrollviews synchronisation issue +4.61
Appcompat library error : No resource found that matches the given... 0.00
Why does AOSP add new APIs to support libraries without adding them... -3.68
Remove everything else after a matched pattern +1.02
Android nested fragments - java.lang.IllegalStateException: Activit... 0.00
How to get back the files removed with `git rm -r -f`? -1.25
Unable to clean project in Android Studio 0.00
How to show the whole line in the window? -2.06
matching everything until the next match -3.74
Merge changes to specific file from one branch to other in git -3.74
What is the point of "create_clock" command in FPGA design? 0.00
How to git stash pop specific stash in 1.8.3? -2.14
How to alternate two always blocks? 0.00
What is the difference between single (&) and double (&&... +3.80
How to bind an interface to multiple ports without duplicating code? +3.89
Are there any advantages to having fewer levels of wrappers in veri... -3.91
How can I see the list of all commits that affect a specific file w... +3.44
What's the best way to create a mask knowing the number of bits? +4.56
forcing a bit in a wire system verilog -3.74
How to detect the posedge of two clocks (asynchronous to each other... -2.00
systemverilog: when to use define macro vs generate +0.25
Connecting Verilog Arrays: Multiple Drivers 0.00