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Rating Stats for

Paul A. Clayton

Rating
1537.08 (13,351st)

Reputation
3,320 (50,875th)

Page: 1 2

Title	Δ
Have a few questions about caches and cache hits/misses	0.00
How to find out available execution units of a processor in Linux?	+3.96
How much data is loaded in to the L2 and L3 caches?	+4.00
cost of x86 register renaming	0.00
Program and Data share RAM and have different word lengths	0.00
What cache invalidation algorithms are used in actual CPU caches?	-1.33
How many levels of pipelining can be acomplished with modern CPUs v...	+0.46
Why would computers transfer data and instructions from main memory...	0.00
Decrease in instructions retired after loop Unrolling	0.00
Memory - Paging and TLB	0.00
Hyper-threading and gaming (and other computing applications)?	0.00
stack or global data (heap) - which one is better for allocating da...	0.00
MIPS Architecture : NOP (No-Operation) Vs Data Forwarding in Hazard...	0.00
Calculating average memory access time in a system implementing cac...	0.00
Input for branch predictor unit?	0.00
what is the advantage of having instructions in a uniform format?	0.00
Off Chip Cache Coherence and L2 cache partitioning in multicores (a...	0.00
MSI: Why do we need to write the line back when other CPU is going...	0.00
MSI/MESI: How can we get "read miss" in shared state?	0.00
Cache Addressing Methods Confusion	0.00
MIPS pipeline timing diagram	0.00
Why speedup reduces with increase in number of pipeline stages?	+4.75
Which architecture to call Non-uniform memory access (NUMA)?	0.00
Designing a virtual memory with TLB	0.00
Hardware Prefetcher prefetches single block or multiple blocks?	0.00
Byte Manipulation for MIPS instruction set	-3.78
Calculating Virtual Memory page table and translation lookaside buf...	0.00
algorithm LRU, how many bits needed for implement this algorithm?	+0.07
Language-Specific Architectures/Processors	+4.25
Is it possible that in MIPS an instruction's certain steps come bef...	0.00
Understanding stalls and branch delay slots	0.00
pipeline stalling and bypassing examples	0.00
Why use 1 instead of -1?	0.00
how do processor knows about the latest copy of cache line in multi...	-4.35
Why is there an alignment bigger than a word?	0.00
Alignment network needed for loads?	0.00
Line size of L1 and L2 caches	0.00
Why is EFLAGS bit 1 always set?	0.00