StackRating

An Elo-based rating system for Stack Overflow

Home | About | Stats and Analysis | Get a Badge

Rating Stats for

VAP

Rating
1453.71 (4,531,545th)

Reputation
435 (305,367th)

Page: 1

Title	Δ
VHDL implementing 2 seven segments at one	-3.04
differential signal to single ended vhdl	+0.50
Iteration limit reached - simple counter in VHDL FSM	0.00
FPGA output pins outputting wrong state	0.00
VHDL state machine with several delays - best approach?	-3.16
VHDL traffic lights FSM using LPM counter: where to set/reset count...	0.00
VGA controller with VHDL	-3.43
How to learn to write VHDL test benches?	-3.54
Why it is necessary to use internal signal for process?	+0.38
Vhdl- Counter has latch(es)	0.00
How to initialize a bit vector in VHDL	-0.45
How to implement clock frequency multiplier using VHDL	-3.10
Unintentional latches in finite state machine (VHDL) + feedback	+2.99
VHDL: signal cannot be synthesized	+0.31
Why is rising edge prefered over falling edge	-0.67
Is the setup time a concern in asynchronous signals in processes?	-0.99
VHDL internal signal to change output - not working?	-3.26
VHDL - Input not used	-3.50
vhdl asynchronous assignment in for loop	-2.24
AND all elements of an n-bit array in VHDL	+2.41
VHDL or verilog SR latch	-3.72
In a state machine process is there a difference if I state specifi...	-3.88
Contruct Moore and Mealy Diagram that complement their input	-2.92
VHDL - Adding two 8-bit vectors into a 9-bit vector	+0.25
VHDL 4-bit binary divider	+0.70
ONE clock period pulse based on trigger signal	-1.20
VGA VHDL Screen Moves when I refresh	+0.33
VHDL Define a signal when undefined	-3.95
Compiling *.vhdl into a library, using Altera Quartus II	-3.68
nbit Bitslice ALU with For/IF Generate in VHDL	-3.55
VHDL state machine differences (for synthesization)	-3.87
Reverse bit order on VHDL	0.00