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Paul S

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1530.04 (18,482nd)
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6,479 (25,008th)
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Mercurial / hg - abort: outstanding uncommitted merges -1.93
How do I get name of an instance using a method operating on it in... +0.45
When are `include directives not needed in Verilog and SystemVerilog? +0.97
Good Practice (for FSMs): BUSY or IDLE +1.19
OpenCL for GPU vs. FPGA +0.46
Design VHDL state machine for initialization +1.97
Best VHDL design practice +0.98
HG Update Branch merge required -1.27
Mercurial equivalent of git whatchanged? -0.29
Division in verilog +1.21
Can I checkout & commit to several Mercurial hg branches at once? +0.45
Do any hardware (ASIC) companies use mercurial (hg) 0.00
How can I estimate if a feature is going to take up too many resour... +2.02
VHDL Clock Divider With Decimals +0.47
About verilog flip flop delay +2.05
OpenCL Less Than Equal and Boolean Vectors -0.50
'Forgetting' a dead-end branch +1.12
Use GPU and CPU wisely +1.12
Source control and working on new version of app -0.24
OpenCL cl_datatypes arithmetic +0.50
Are GPU's limited in their ability to do larger calculations? -0.72
A Strange Computer : Cache based computer 0.00
how to turn off hg status -S +1.91
Why dead code in OpenCL kernel influence result in Nvidia GTX550ti? 0.00
Sum Vector Components in OpenCL (SSE-like) 0.00
OpenCL constant memory caching 0.00
(Mercurial/tortoisehg) Lost commits - how to troubleshoot +0.36
Mercurial: How to push a bookmarked changeset which creates a new r... 0.00
VHDL Method Call +0.59
VHDL If Statements -2.55
16-bit numbers multiplication 0.00
Creating an array in Verilog using ModelSim 0.00
Mercurial one head, two deviations +4.05
Python 3.2 for-loop +0.10
Long time between submit and start time of a command in OpenCL 0.00
is it worth rewriting my code in cython? -0.25
Looking for a simple hash table implementation example to use as a... 0.00
VHDL - How to detect change on std_logic_vector? +3.60
Dealing with clock in Synopsis tetramax 0.00
Git and Mercurial: what would be equivalent of Git workflow in Merc... +4.24
Understanding this T Flip-Flop example? 0.00
what is the most efficient way of moving multiple objects (stored i... -4.15
In VHDL when is the right time to use a Process statement? +1.02
Assign a synthesizable initial value to a reg in Verilog -2.34
VHDL Procedures +4.22
Are advanced VHDL configurations ever used in real life? +3.85
vhdl ram module and use of registers +2.09
Is there a better way to re-write a BCD_counter in VHDL code with l... +2.10
Calculations with Real Numbers, Verilog HDL 0.00
How do I apply command line overrides to SystemVerilog ovm_sequence... -0.15