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Rating Stats for

fru1tbat

Rating
1530.03 (18,496th)

Reputation
1,496 (109,302nd)

Page: 1 2

Title	Δ
Convertidor Binary to BCD	-0.35
near "when": syntax error in VHDL	0.00
Ambiguous type in infix expression VHDL	0.00
How to determine if more than one bit in an STD_LOGIC_VECTOR is set...	+1.88
BCD adder of 4-BCD-digit numbers in VHDL	0.00
How to concatenate 3 operation select bits in a 4-bit ALU design -...	0.00
ModelSIM ALTERA error	0.00
Compare std_logic_vector to a constant using std_logic_vector packa...	-0.96
Value U is missing in select	0.00
Unable to synthesize a signal because of bad synchronous descriptio...	0.00
I am trying to pipeline a 8x8 2s complement multiplier and I don...	0.00
vhdl: too many actuals for block...with only 0 formals	0.00
Why Quartus II recognizes my variable as a signal?	0.00
VHDL short form to trigger actions on raising edges	-1.98
Using Generate in Vhdl	+3.59
Converting 8 bit binary to BCD value	0.00
VHDL If/Else statement	+3.67
Is it possible to use synchronous process in functions?	-4.33
VHDL - Increment with one (unsigned)	+3.72
need to use std_logic_Arith with std_logic_signed/unsigned	0.00
VHDL synthesis of if statements without elsif and else condition	-1.84
Cause of gated clock	+3.74
Is it possible to use a process inside a 'case is when' str...	+2.62
My inputs keep being ignored in VHDL	-3.47
VHDL code mathematical function	0.00
Unsigned literals in VHDL	0.00
VHDL Input & output code	0.00
VHDL. Alternating between components every other clock cycle	0.00
Can a constant expression ever be valid in a VHDL case statement?	+3.91
How can I extract elements from a record using an integer reference...	-1.75
VHDL FSM Implementation using port mapping	0.00
Baud Rate Clock VHDL -- floating point exception error and/or style...	+3.68
The code which i posted is I2s code \| I'm having the same error...	-0.06
Modelsim / reading a signal value	+3.99
Vhdl rising_edge statement not synthesizable	-0.01
vhdl function package test	-3.38
"near then expecting <= " what is this error?	+0.65
Structure of VHDL code for barrel shifter with behavior architecture	-1.85
Can I use port mapping in behavioral method and is using process co...	-0.06
Vhdl ERROR that I don't understand	0.00
wait on an untimed signal in VHDL testbench	+3.12
VHDL: Using an unsigned Case selector	-0.04
Trouble running decimal numbers on 7 segment	-0.11
VHDL code help- output once cycle earlier	0.00
Trouble having port mapping two modules in one	0.00
VHDL: Zero-Extend a fixed signal value	+4.72
VHDL error please	-0.21
VHDL Dual Port RAM unexpected latches generated	-0.20
VHDL beginner - what's going wrong wrt to timing in this circuit?	-0.20
MATH_REAL log2 function	+3.88