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Rating Stats for

Prashant

Rating
1500.62 (437,253rd)

Reputation
175 (502,739th)

Page: 1

Title	Δ
Does time delay in a sequential logic circuit block have a influenc...	+4.07
Verilog model sim	+0.21
Implement a 32x64 register file in Verilog	0.00
Debugging test bench, StX outputs	0.00
64 bit LFSR output in verilog	0.00
Implementing a 2n-bit comparator using cascaded 2-bit comparators	0.00
network-on-chip verilog code	0.00
I want to use the ram in my FPGA Altera DE1-SOC, am I taking the co...	+4.32
Execution interrupted or reached maximum run time in edaplayground	-3.95
Altera Quartus falsly says Modelsim isn't installed	0.00
Syntax error in Testbench file	-4.03