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Hida

Rating
1519.30 (33,368th) 		Reputation
708 (206,062nd)
Page: 1
Title Δ
Simulating VHDL Modelsim Dual-port RAM with 2 Clocks 0.00
Read after Write Latency in Asynchronous FIFO? -0.23
Verilog: Aligning valid and invalid bytes from a dynamic input +3.73
systemVeilog - pass array of unknown size 0.00
swap two variables in verilog using XOR -2.22
Assign reg which has initial value 0.00
How to change the code. 16bit CLA (carry-look.ahead adder) verilog... 0.00
Synthesize-able delay in Verilog +0.57
I2S Transmitter Verilog Implementation not working +3.84
System Verilog Implementing flags out of always_comb block 0.00
Verilog function result different from expected 0.00
Declaring an array of constant with Verilog +3.94
Verilog Module Instantiation and empty begin end +3.85
How can I determine the register bit widths correctly? +2.08
How to assert a property is false at every clock cycle? +3.52
Checking a circuit for errors 0.00
How to achieve signal connection depends on macro's value (`if... 0.00
Verilog Program Counter with branching +0.04
module selection in verilog 0.00
How to write a module with variable number of ports in Verilog +2.97
Verilog always@(..) output not working as expected 0.00
system verilog assertions: Using a reg value in a repition operator 0.00
verilog timing error happens in I2C design 0.00
Pack individual signal into an array -3.37
How can I set a delay in Verilog using a clock? 0.00
UVM sequences producing related numbers +4.01
How to execute task concurrently with other statements in an always... 0.00
7 Segment Display multiple conditions verilog 0.00
printing "still alive message" only once for multiinstanc... -3.42
Modelsim Testbench not generating console output 0.00
Multiple Clock Assertion in Systemverilog 0.00