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seldridge

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Chisel/FIRRTL DefnameDifferentPortsException 0.00
How to make verilog is ready for CAD tools after build the VCS simu... 0.00
What FPGA vendor boards are supported (well) by Chisel? +3.77
How to call the variable defined inside withClockAndReset 0.00
does the Chisel/FIRRTL toolchain do boolean expression optimization? 0.00
How to define output Reg in Chisel properly 0.00
How do I create a C/C++ preprocessor style macro in Chisel HDL? 0.00
What would be the best way to initialize a Bundle Register to all 1... 0.00
How to get the Index of Max element in UInt Vec , Chisel 0.00
How do I write to a conditional output +3.99
how to override/extend chisel signal naming 0.00
Maintain connection order on FIRRTL using Cat operator +4.03
Is it possible to test chisel Reg() in console? 0.00
Use FIRRTL Annotations to connect multi-bit wires and pins 0.00
How to do parallel testing with peekpoketester in chisel3? 0.00
Error while building sodor emulators, riscv-sodor 0.00
How to count time in chisel with iotesters? 0.00
Printf in Chisel PeekPokeTester behaves differently from verilator... 0.00
How do you test RawModules? 0.00
firrtl.Driver is deprecated - but what should we use instead? 0.00
How to duplicate a single bit to a UInt in Chisel 3? 0.00
comparing the value in a register to an int 0.00
How to decipher comments in generated Verilog from chisel? 0.00
How to import getVerilog() function from the bootcamp examples? 0.00
Firrtl runs of out of heap memory with large input 0.00
What do the (site, here, up) arguments mean when creating rocket-ch... +3.87
What is the meaning of :*= and :=* operators? +4.00
How to config xLen in rocket core? 0.00
Chisel Output with SystemVerilog Interfaces/Structs 0.00
Vector of RegEnable 0.00
What benefits does Chisel offer over classic Hardware Description L... 0.00
How to add reset to the Queue chisel class +3.95
When we should use ":=" not "=" in chisel3, sam... 0.00
What is the purpose of TransitName in Chisel3? 0.00
How to specify chisel’s post-processor? -3.88