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Rating Stats for

pwolfsberger

Rating
1499.80 (3,742,532nd)

Reputation
338 (374,400th)

Page: 1

Title	Δ
vhdl std_logic not declared error	0.00
VHDL create a vector of alternating zeros and ones	+4.30
Use dma transfert with Cyclone V Avalon-MM for PCIe	0.00
Sorting network in VHDL	+0.26
VHDL Parametric case	-1.73
vhdl error 827: signal <> cannot be synthesized	-3.66
VHDL How to convert std_logic_vector (one variable of Nbits) to std...	+0.18
How to transfer two 64 bit from the nios to VHDL using the avalon b...	0.00
How would I do something like this without a synchronous error in v...	0.00
Why is this Shift Register not loading properly in VHDL?	+3.90
Testbench for T Flip Flop using D Flip Flop in VHDL	-3.89
'last_event VHDL equivalent in verilog	-0.07
Design does not fit ispLEVER	+0.13
When I try to open a project, Quartus opens and then closes itself	0.00
VHDL - unconnected components in top module	+0.38
if statement not working as expected in vhdl	0.00