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Marty

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1548.81 (8,295th)

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5,171 (32,031st)

Page: 1 2

Title	Δ
verilog basic compiler error	0.00
VHDL gate basics	-2.53
How do I use a Unix script to select a Verilog test file?	-0.10
Verilog doesn't have something like main()?	-1.96
Why is there no assign statement in this Verilog function?	0.00
Verilog linting tools?	-1.59
How to interpret blocking vs non blocking assignments in Verilog?	-3.41
Modelsim: how to setup 27 MHz clock	-2.33
Preserving the widths of ports	+3.86
Verilog to GDSII compiler (open-source)	+3.34
How to sign-extend a number in Verilog	0.00
does systemverilog support linked lists?	+3.59
Simulation not working - port mapping wrong?	0.00
Basic Verilog question: shift register	+3.95
VHDL constant initialisation	-0.03
Complex floating-point sequential logic in Verilog	0.00
How to declare and use 1D and 2D byte arrays in Verilog?	+4.16
Signals and Variables in VHDL (order) - Problem	+3.83
converting if else statement to ternary	+1.63
output not updating until next clock cycle	0.00
Global declarations are illegal in Verilog 2001 syntax!	0.00
Great computer-science speeches	-1.46
How to synthesis verilog cores made in xilinx core generator?	0.00
Syntax for using an array of wires as input	+4.17
verilog modelsim fpga	+3.01
Producing a clock glitch in a verilog design	-3.98
VHDL - When does a process() run for the first time?	+3.91
How to 'assign' a value to an output reg in Verilog?	+3.95
How to generate serial signal from string?	+4.11
Verilog: Can you put "assign" statements within always@ o...	+4.04
How to share register and bit field definitions between a device dr...	+0.08
compute results and mux or not	-3.81
Using SOS, it possible to merge all files in a branch to the trunk...	0.00
Flip-Flop triggered on the edge of two signals	0.00
Program for drawing VHDL block diagrams?	-3.82
How to generate pseudo random number in FPGA?	+4.00
Why is XST optimizing away my registers and how do I stop it?	0.00
task in verilog	0.00
FPGA based RTL evaluation	+1.34
How would you implement this digital logic in Verilog or VHDL?	0.00
How do I read back in the output of Data::Dumper?	0.00
Whats the BEST way to setup a library to support links into precomp...	-0.12
Efficient synthesis of a 4-to-1 function in Verilog	+2.25
Verilog automatic task	-3.90