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Rating Stats for

CJC

Rating
1481.96 (4,488,600th)

Reputation
509 (269,360th)

Page: 1

Title	Δ
What is the best way to detect pulses between two clock domains?	-4.10
Xilinx Vivado: Block Design, Address Range of each module end point	-3.88
Best Route For Input Clocks on Kintex7 FPGA	0.00
Making a serial in serial out adder	0.00
VHDL design - creating if loop within second process not working	0.00
display 3-bit on 7 segment display	-3.89
Reading a ConfigurationSection	-0.13
The value for an unsigned byte was too large or too small	+4.12
How to properly run an FFT on a windowed set of data from a pure si...	-3.43
How to overload/substitute/extend C# Interface used in common code	+5.17
How can I deploy a C# console application as a single exe?	+0.23
VHDL Vector passing	-1.44
Reading properties using reflection	0.00
c# SerialPort: how to send "0 byte" transfers (AKA ZLP: z...	0.00
c# Socket send receive network	0.00
A proper way of defining methods strongly connected to the interface	-3.95
Case statement vs If else in VHDL	-3.08
VHDL: Using hex values in constants	0.00
Trouble using a variable as boundary in a std_logic_vector with the...	0.00
Trying to find Fmax in VHDL but getting extra cycle of delay	0.00
How do I solve this delta cycle clock delay issue	0.00
edge detection of signal in vhdl	-3.87
Figuring out the size of the counter with a 50Mhz clock	+4.29
How to access the table from the Data Source in C#?	-4.14
ERROR:HDLCompiler:806 - Line 35: Syntax error near "function&q...	+0.06
Memory map instruction/data memory in VHDL.	0.00
Vhdl Multiplier usage too low	0.00
Modelsim error message "Can't open file"	0.00