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Rating Stats for

Amir

Rating
1504.07 (190,869th)

Reputation
415 (317,294th)

Page: 1

Title	Δ
Easy way to assign values to an array in Verilog?	0.00
Why is this variable not considered a constant?	-0.11
Design a shift register in VHDL	+4.00
delayed signal cause unexpected behavior in VHDL	0.00
Initializing arrays in Verilog	+0.03
Advanced verilog design analysis	+0.06
How to write a 32 bit "reg" of a ".v" program i...	0.00
feedback on mux in verilog	+4.28
16 bit adder using 2 bit adder as component	+4.33
How can I design VHDL modal in the following details?	-3.18
why is the output of JK flip flop red in simulation?	+4.21
What is the wrong with my verilog code?	0.00
How do I make a 16 bit Adder-Subtractor with Overflow detection usi...	0.00
Error loading design modelsim PE student edition 10.4	0.00
Cannot understand the errors in my code	-1.77
Is N-1 the largest term which could be used for Generic in VHDL	-3.99
how to call a value from VHDL code file and put it in another code...	0.00
Mapping buffer port in VHDL	+0.04
VHDL syntax issue	+0.17
Synthesis: Implementing a delay signal using a counter on power-up...	-4.00
Instantiating 4 bit Full Adder	0.00
50 MHz to 64KHz frequency	0.00