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Rating Stats for

Barry Moss

Rating
1486.30 (4,460,593rd)

Reputation
389 (334,188th)

Page: 1

Title	Δ
Synthesis of two simulation identical designs - with and without se...	0.00
How do I write this verilog testbench?	-3.87
Verilog XST ignores hard coded input values	0.00
malformed statement in verilog3	-1.85
Cause of unconnected node warnings in verilog code	0.00
how to check output of 7 segment display written in verilog	0.00
How to minimize route time in verilog code	-0.16
What is the merit to using the negedge clock in verilog?	+3.92
Infrared output in verilog	0.00
Verilog FIR filter code error	0.00
How to make an array in 'verilog' (code inside)	0.00
Dealing with lots of outputs in a finite state machine verilog	0.00
Error Number 10170 in Verilog using If/Else and Case Statements	-3.49
How can I improve my code to reduce the synthesis time?	-4.27
How to check data one cycle later in Verilog?	+4.23
How to Map the clock in RTL synthesis with memory?	0.00
Using single ended port in logic expecting diff-pair?	+0.70
Verilog: error instantiating module	+0.02
How can i instantiate a module inside an if statement in verilog?	-3.91
Why is this variable not considered a constant?	+0.11
FPGA large input data	+4.09
Do all Flip Flops in a design need to be resettable (ASIC)?	-1.38
how to use dynamic variable in xilinx	0.00
verilog compiler error: near “;”: syntax error	-3.74
verilog if-statement hardware translation	-4.03
Verilog Synthesis: Reg vs Reg+Wire for Module Instantiation	0.00
System Verilog Initial process compilation error	-0.05
generalize state machine in Verilog for N bit	0.00
Verilog Vending machine FSM	0.00
segment BCD to 7 decoder in verilog	0.00