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Rating Stats for

Rama Krishna Meda

Rating
1485.29 (4,468,628th)

Reputation
16 (1,735,902nd)

Page: 1

Title	Δ
Nested conditional operator / mux syntax	-3.14
Translate conditional operators in Verilog	0.00
How to write this for loop conditions in Verilog design correctly?	0.00
Verilog HDL always & case errors	+0.86
How to get latch with blocking assignment?	-1.52
I`m trying to implemet 4 buffers in Verilog and I have some warrnings	+0.13
Not getting the relevant output in my 32-bit ALU using gate-level v...	+0.09
Error in the output window of Xilinx as shown in below diagram for...	+4.18
Procedural assignment to a non-register shiftedy is not permitted,...	0.00
Verilog: assigning value to reg	-1.77
Verilog: Given clock is 10ns, how long does it take to add 1 to 10...	0.00
How do I save key-press entries on a PMOD keypad for FPGA	0.00
when i perform synthesis getting warning Line 49: Result of 9-bit e...	-3.74
Does the following verilog code have a race condition issue?	-4.12
Vivado just points out that there is an exception	0.00
Problem outputting solution for a 2 digit BCD adder using Verilog	0.00
Access from design wrapper to variables of own IP block in Vivado (...	0.00
Setting entire register array to zero	-1.62
How to do Verilog variable part select with % on both sides of colon?	-4.04
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer c...	0.00