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Rating Stats for

Philippe

Rating
1529.86 (18,638th)

Reputation
3,104 (54,462nd)

Page: 1 2

Title	Δ
mixed VHDL & Verilog designs: which free simulation and/or synt...	+1.53
VHDL - creating a variable number of signals	+3.84
Output of my VHDL code is becoming reset dependent	0.00
Error in my VHDL code, but I can't seem to figure out why	-2.43
changing control variable in Case statement in VHDL	+3.90
Warning "has no load", but I can't see why	+3.67
if statement in VHDL	-0.30
VHDL inout ports	+1.55
VHDL Procedures	-4.22
Behavior of VHDL comparison operator with integer argument	+3.55
FF/Latch and other warnings	+3.67
Regex for VHDL string literal	+3.71
How to declare an output with multiple zeros in VHDL	0.00
How to detect compiler	-0.29
Vhdl vector boundry check	-4.52
VHDL - Undefined behavior in my key detection	-3.19
Hexadecimal number on seven-segment	+0.14
convert integer to std_logic	+1.81
Makefile - two different targets	-3.55
Is initialization necessary?	+4.04
necessity of 'event	+3.54
VHDL and using the 'report' Statement	+4.26
VHDL: Errors in FlipFlop D code	-1.49
VHDL generic parameters for entities	+4.32
VHDL entity and architecture design	-1.71
Implementing a FSM in VHDL	+3.88
Use a generic to determine (de)mux size in VHDL?	-2.02
Indexing arrays in VHDL	0.00
Glib casting macros	0.00
As a command it runs fine from cmd prompt but not from java code	+2.98
create two elements connecting to one mux 41 and 21	-3.72
How to do a VHDL "typedef"	0.00
Infinite loop, won't end with while loop	-3.09
How does signal assignment work in a process?	+3.74
Simulation vs hardware mismatch	+3.92
VHDL: How to convert a floating point number to integer	+4.57
Whats wrong with this VHDL code	+0.16
What to use for VHDL/digital-logic simulation on Mac OS X	-3.11
Subprocedure call in VHDL	+3.88
what is the convention for the location of my bash scripts?	+0.43
Shuffling a 2D array in Java	-3.84
Universal shift arithmetic right in VHDL	+4.11
software simulator to practice vhdl	+3.81
Making a 4-bit ALU from several 1-bit ALUs	+4.02
"Serialize" VHDL record	+4.12
State to std_logic	-2.15
Simple State Machine Problem	+0.11
Hidden Features of VHDL	0.00