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Rating Stats for

Nathan Farrington

Rating
1499.71 (3,757,869th)

Reputation
1,293 (124,205th)

Page: 1

Title	Δ
Simulating MIPS processor on FPGA using Verilog	+4.03
Assign a synthesizable initial value to a reg in Verilog	+2.13
Verilog gated clock source in Xilinx	+0.08
Are there any good dependency management tools that aren't language...	0.00
< bit half-byte byte ... > memory access in 32-bit memory usi...	0.00
fixing bit width mismatch	+0.52
Always block being ignored	+4.37
How to put a 2 sec counter in a for loop	-1.58
Schematic editor for digital designs	0.00
verilog always, begin and end evaluation	-3.92
Spartan 3 Starter Kit Constraints File	-0.17
Verilog Best Practice - Incrementing a variable	+0.06
24 bit counter state machine	-3.20
Reduce delay by understanding Xilinx Synthesis report	-4.11
related to List (want to insert into database)	-4.11
web development using java	+4.00
Should SVN repository include IDE project files?	-3.19
Portable binary representation of date/time value	-1.91
Combinational implementation of hashing algorithms	+4.45
"ERROR: broken data stream when reading image file" (True...	0.00
Flow based routing and openflow	+3.99
Pythonic way to check if a list is sorted or not	-1.72
Portable makefile creation of directories	0.00
Configuration Management for FPGA Designs	0.00
Should I create each class in its own .py file?	0.00