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Rating Stats for

Sourabh

Rating
1451.36 (4,532,273rd)

Reputation
310 (401,657th)

Page: 1

Title	Δ
verilog code to find a single max value for an input that has 1000...	+0.51
Illegal left hand side of blocking assignment	-3.03
Sum of Values based on bits enabled Verilog	-3.23
Verilog code for wighted average circuit	-2.89
Using reg output as input Verilog	-3.39
Verilog code generating 'dont care' for iterations	0.00
Test for connectivity between two points in a schematic	0.00
Test Bench code won't work in verilog for pipelined processor	0.00
crc ip hdr checksum in verilog	+0.65
conditionally calling a module using case statement	-3.54
How to initialize contents of inferred Block RAM (BRAM) in Verilog	-3.51
When should I use reg instead of wire?	-3.72
addition not working in for-loop verilog	0.00
synthesis and Implement RTL design in verilog	0.00
define a constant in verilog (for synthesis)	0.00
while loop inside a for loop	+0.32
Error in verilog, coding for CSHM Filter using generate statement	-3.09
Verilog - When would it be useful to manually set an output to high...	0.00
How do I assign one multidimensional array to another in system ver...	-3.70
In verilog Part-select of vector reg array is illegal	-3.63
Is it written in VHDL or Verilog	-3.79
Verilog error while declaring a array	-3.28
Pass parameters in Verilog	+0.29
Push button link with blink LED	-3.69
Verilog promote one-bit wire to 64-bit bus	-2.94
Unable to elaborate instantiated module in verilog	0.00
What is the difference between = and <= in verilog?	-2.98