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Rating Stats for

kraigher

Rating
1507.38 (105,539th)

Reputation
585 (240,906th)

Page: 1

Title	Δ
VHDL Structural	0.00
wait until rising_edge(clk) vs if rising_edge(clk)	+0.02
Using Custom Packages Causes Circular Dependency	+4.29
Testing FPGA Designs at Different Levels	-4.40
Array of values loaded through UART in VHDL	-2.84
Emacs auto indenting does not support the VHDL 2008 generic package...	0.00
Modelsim simulation starting and ending time	+3.92
Simulating .xci Files in Questasim	0.00
VHDL textio, reading image from file	-1.81
vhdl package signals modelsim wlf	0.00
Aldec Active-HDL: vlib in GUI gives "Warning: Cannot create li...	-0.10
VHDL OR logic with 32 bit vector	0.00
How to wait for Modelsim Simulations to complete before proceeding...	+4.12
VHDL Assert - actions other than report	+4.17