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Rating Stats for

sharvil111

Rating
1549.43 (8,120th)

Reputation
3,457 (48,779th)

Page: 1 2 3

Title	Δ
how to force data in design instead of using testbench	0.00
The left-hand-side of continuous assignment is illegal	0.00
SystemVerilog: Creating packed arrays using variables	0.00
How to define time unit and time precision in system veriolg	0.00
Can I write a cover group/Cover point on internal variables/registe...	0.00
What is the exact criteria for an inout port, when sometimes inout...	-2.63
What is the best way to give name to different cases in Verilog?	-0.03
Ring Counter in Verilog	+3.82
Implementing one-bit flags in a 32Bit ALU using Verilog	0.00
how to pass vector to module without changing value?	-0.04
SVA Repetition Non-Consecutive Operation Qualifying Event	+3.92
verilog Linear feedback shift register random	0.00
Confused with ripple carry adder output	0.00
carry lookahead using structural verilog	0.00
Creating ROM in verilog without using Block ROM	-0.02
Malformed statement Verilog	+3.87
initialize systemverilog (ovm) parameterized class array	0.00
Non-constant indexing for a logic statement in systemverilog	0.00
Unsigned reg subtraction in Verilog	0.00
Module not properly instantiated?	0.00
Errors in benchmark code	0.00
Can't get my head around testbenches	0.00
JK Flip flopError	-0.72
Execution in verilog sequentially or concurrently	+4.51
Error while using always block in verilog	0.00
verilog assigning to same variable not working	0.00
Declaring Variable in Verilog with Indexing that doesn't start...	+0.51
Syntax Error in verilog	0.00
Why does an If statement cause a latch in verilog?	-1.23
Can we can have print statement in classes without any function/tas...	-3.12
1second down counter with initial value verilog code	0.00
how to get the number of elements in an array in systemverilog?	+3.75
Using display in verilog	-3.92
array input never used	0.00
If-else condition for n-bit number	0.00
verilog if-else error message	0.00
Constant latency for any function?	0.00
wire in always block/case statement - Verilog	+3.93
Use of Non-Blocking Assignment in Testbench : Verilog	+4.57
Verilog program won't read input	0.00
Verilog Design of a 32-bit ALU	+4.65
fgets() behaves unexpectedly	0.00
Single Instance	-2.15
System task or function '$value$plusarg' is not defined -&g...	+0.60
What is the difference between reg and wire in a verilog module	-4.12
Verilog - Do I need to add delay with two always situation and also...	0.00
Verilog Synchronous state machine	0.00
Verilog coding errors	-3.85
why output of a module can't reach from outside module	0.00
Execution interrupted or reached maximum run time in edaplayground	+3.95