StackRating

An Elo-based rating system for Stack Overflow

Home | About | Stats and Analysis | Get a Badge

Rating Stats for

Light

Rating
1508.22 (86,598th)

Reputation
193 (472,733rd)

Page: 1 2

Title	Δ
Vim, How to create key bindings to: shift, ctrl, alt, cmd keys?	+3.95
how to solve the illegal reference error from verilog	0.00
I got a lot of error when trying to tranfer my verilog code from mo...	0.00
How to remove the last empty line in vim?	0.00
ALU test bench using test vector file not working	0.00
Efficient way to format curly braces to be inline	+4.10
Error while using always block for half adder: sum is not a valid l...	0.00
vim search with * regexp is not benefiting required results	0.00
How to connect enable port to 4x1 MUX in verilog?	0.00
Why my behavioral simulation failed even the text editor didn't...	0.00
BCD adder in Verilog code , I don't know my error	0.00
keep getting these error messages..compile error	-0.00
How to create .vim/colors?	-0.13
Verilog 4-bit comparator structural model	0.00
Excel nested if function returns false or true instead of a numeric...	0.00
I am getting unknown value when doing a 4 bit shifter verilog (gate...	0.00
Simplify the boolean expression F=(Not B and Not C) or (B and Not C...	-4.09
Keep cursor line vertically centered in vim	+3.90
jedi-vim how to close __doc__ window and remove from buffer list?	0.00
GREP: Excluding file names with specific pattern while including sp...	+3.29
How to change clock in Verilog?	0.00
verilog errors (13069) and (13205). Happens when using `define	0.00
Put a case value in the middle of a sentence (formula)	0.00
To make output LED blink in moore machine	0.00
Why after the while loop I am only getting last row value?	-0.11
Execute Always Blocks with same value	0.00
Calling a Module in Verilog	0.00
Designing counter on Verilog with input button	0.00
Does ethernet communication need internet connection?	-2.43
Implementation of 8:1 MUX using 3:8 decoders and 2 input gates	0.00
How to switch modules in verilog?	0.00
Check last row every iteration in a for loop	-2.03
How can i show a VBA UserForm automatically when Excel workbook ope...	0.00
Boolean Algebra expression simplification with mulitple theoerms	0.00
system verilog HDL - 4bit input logical calculator	0.00
How does this hardware increment register addresses for 32-bit valu...	0.00
how to implement verilog code with small modules	+4.03
VHDL compliling error Testbench (ModelSim)	+0.03
Logic gates solving vs Simulations	0.00
Verilog: Can the same register be referenced more than once in an a...	0.00
Find all lines with at least 3 special characters in string using R...	+1.96
How to realize "posedge asynchronous reset logic" in veri...	-1.99
Why does registers exists and how they work together with cpu?	+4.16
JK-flip flop using gate level description in Verilog give me a timm...	0.00
Verilog: More efficient way to use ternary operator	+2.14
Excel formula to extract the part of a string that is before the se...	0.00
Exclude elements of a list that are in another array	+6.52
If all rows in any column are blank then delete entire column + ski...	-2.75
save hash in csv file under particular header	+2.78
Regex for numbers like 1.1.1	0.00