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Rating Stats for

Martin Zabel

Rating
1512.30 (56,050th)

Reputation
3,141 (53,784th)

Page: 1 2 3

Title	Δ
FSM 2 process VHDL	0.00
Have Excel Show Numbers instead of text	0.00
VHDL code works in ModelSim but not on FPGA	-0.68
How to deal with signals in process statements	0.00
Detect changes in std_logic vhdl	0.00
Binary fixed point multiplication	0.00
Generic Multiplexer warning	0.00
Checking if an array of structures is 'empty' in C	0.00
AMD APP SDK (OpenCL) doesn't detect AMD CPU	0.00
Difference between cl_context & cl::Context	+3.01
Quartus II use file only in simulation	0.00
Warnings inmatrix multiplication in vhdl	0.00
C++ code on Android - execl() function call failure	0.00
OpenCL clCreateBuffer() crashes the program	0.00
OpenCL - Writing to the Buffer is zero?	0.00
vhdl signal default value	+1.69
ModelSim and SignalTap do not show the same signal level	0.00
VHDL Multiple Processes error	+3.31
VHDL behavioural D Flip-Flop with R & S	+4.01
Test bench file for integer types	0.00
copy or assign one string to another string in a 2 dimensional arra...	+0.27
c passing pointers to functions to handle char arrays and data	+3.61
MPI_Gather() the central elements into a global matrix	0.00
MPI_Gather 2D array	0.00
Calculating the Overflow Flag in an ALU	+3.73
Unable to write on /dev/* files	0.00
_mm_sad_epu8 faster than _mm_sad_pu8	0.00
Using Fixed point in VHDL	0.00
Where does the Xilinx TCL shell emit the results?	0.00
Alternative method for creating low clock frequencies in VHDL	-3.51
Include a Makefile as if I'm in another directory?	0.00
VHDL code behaves abnormally after synthesis (I2C)	0.00
Why the second scanf() input string is ignored	+0.07
Passing submatrix between processes	-3.00
Adding header files in Verilog	+3.67
cross total of a std_logic_vector	0.00
Using BUFG to drive clock loads	-1.18
Simultaneous reading and writing to registers	-4.37
copy data from kernel space to user space	0.00
Independent Nexys 4 clocks desynchronizing over time	0.00
how can I move a background proces to foreground	+3.46
VHDL - library doesn't work	0.00
Pointers, counter gets confused	+3.73
I can't figure out why I'm getting an undefined reference i...	+3.74
VHDL inferring latches	-3.51
Gated Clock in Clock Divider for a Square Wave	+4.55
Space efficient data bus implementations	-4.11
Bidirectional to bidirectional in VHDL	+4.00
Bidirectional to bidirectional in VHDL	-4.00
VHDL Place and route path analysis	0.00