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Rating Stats for

Krouitch

Rating
1485.88 (4,464,148th)

Reputation
446 (299,500th)

Page: 1

Title	Δ
Git stash in a pre-receive and post-receive hook does not work as e...	0.00
Arrays of interface instances in SystemVerilog with parametrized nu...	-0.99
Verilog (assign in always)	-0.13
How to get synthesizable delay in verilog	-3.90
Verilog error: XXX is not a constant	0.00
Whether $display syntax works during post-route simulation in veril...	+0.03
iverilog syntax for include?	0.00
generating random the same numbers in verilog issue	0.00
Verilog: wait for module logic evaluation in an always block	0.00
Logic behind Verilog code	-3.70
Synthesizing SV inteface dereferencing ports	0.00
Verilog to SystemVerilog conversion	0.00
Solving Metastability Using Double-Register Approach	0.00
How to use the input's values in "always" definiton i...	-3.26
Using 'assign' for binding module ports	-3.32
Asynchronous reset D flipflop code syntax error	+3.96
unable to enter if else statement	+0.36
when module assign value to the variable, It shows xxxxxxxx	0.00
Verilog if statement assign error	0.00
Error (10170): Verilog HDL syntax error at final_lab.sv(46) near te...	+0.06
Initialize an array using size defined by parameter in verilog	+0.57
Using " * " for multiplication of binary numbers, only gi...	0.00
What is the implication of not resetting a register in reset aware...	0.00
Indexed part select synthesizable in verilog	-3.81
Line break will count as a sentence in python	0.00
Eclipse project building error	0.00