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Rating Stats for

jarno

Rating
1502.79 (334,523rd)

Reputation
129 (610,519th)

Page: 1

Title	Δ
D flip-flop synthesizable	0.00
VHDL - how does "reset" work and how to use?	-2.08
VHDL flip-flop reset different than 0	0.00
Debugging of 128 point FFT	0.00
VHDL 33.3 Mhz clock generated from a 50 Mhz clock	0.00
Counter 4bit with synchronous load and enable and asynchronous reset.	+0.22
Why isnt this code in vhdl simulating anything?(testbench and design)	-0.19
Using VHDL to generate many parallel processing unit	0.00
VHDL - Port mapping - Map different ports of a component into diffe...	0.00
Verilog Subtraction and addition	-0.05
Synthesisable Fixed/Floating points in VHDL's IEEE Library	+3.99
VHDL and clocks 50Mz to 25Mhz	+0.91