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Rating Stats for

Prakash Darji

Rating
1495.69 (4,242,114th)

Reputation
891 (170,355th)

Page: 1 2

Title	Δ
Import data in Verilog	0.00
What kind of assignment is this?	0.00
Error using for loop [procedural assignment to a non-register i is...	+4.19
Assistance on function call in verilog	0.00
Which constructs in Verilog can contain function?	-3.71
How the levels of abstraction of modelling justified in vhdl/verilog	+0.23
How to modify the Verilog code to avoid syntax error?	0.00
Code for non-resetable flop	+0.44
Tell me what's wrong with this code	0.00
verilog code to find a single max value for an input that has 1000...	+3.83
Kind stuck on the output when the output overlap	+4.07
How can I convert an location id in a trie to its position id ? Ver...	0.00
Verilog array assignments	0.00
Designed memory unit doesn't work, cannot read memory 0	0.00
Why does the following redeclaration error happen in verilog?	-3.21
Verilog : Is there an idiom for an incrementing compile-time counter	+0.02
Why on a wire with delay, sharp voltage change at one end will not...	0.00
In Verilog, I'm trying to use $readmemb to read .txt file but i...	+4.16
Verilog Program when I compiler in VCS getting correct output but w...	0.00
Using Verilog parameters in if else conditions	0.00
EX_MEM latch of MIPS pipelining	0.00
ADC with 2s complement output	0.00
How can i get Audio Stream input as binary number for AES encryptio...	0.00
Data memory unit	-3.41
Prime number detector between 0 and 101, digital logic karnaugh map	0.00
Find the longest sequence of ones in 32 bit sequence in verilog and...	0.00
how to write test bench for slave module in which it assign input v...	0.00
Condition: Logical state of multi-bit packed array	+0.48
verilog loop with define macro	0.00
How to initialize contents of inferred Block RAM (BRAM) in Verilog	+0.17
can i call task from from always block in verilog	+0.73
Converting this schematic to verilog code, compile unsucessful	-3.71
I want to Accumulate resulting values, but can't initialize the...	-3.56
How to view the contents of a megafunction RAM from Quartus after s...	0.00
Confused between latch and flip-flop	0.00
What exactly does it means the Argument in the always @ ( ) express...	-1.55
Why is there a difference in Output when using Event Control Statem...	0.00
How do you split long lines of code in verilog?	0.00
What does "quality of result (QoR)" cover?	-3.87
Implement a function using Boolean Circuit	0.00
How to communicate three (or more) modules in Verilog?	0.00
How to instantiate megafunctions in Alteras Quartus-II FPGA IDE	+4.04
Calculate coordinates based on distances	0.00
timing for ASIC design, proper clocking for an D/A	0.00
Accessing register depending their address	+0.24
Designed a D FF using Strucural Verilog but the Q output is showing...	-2.65
Verilog 4x16 Decoder outputs wrong data	-3.84
how to create lines of text with increasing numericals in gvim	-1.20
How to use multiple outputs over time?	0.00
errors in modelsim verilog compile	+4.70