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wjl

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1510.57 (67,131st) 		Reputation
5,734 (28,571st)
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Title Δ
Xilinx True Dual Ported RAM with different aspect ratios on two ports -4.07
Python:How do I use "or" in a regular expression? +0.63
Can I use git-svn to clone a specific branch of a remote SVN repo a... 0.00
VHDL inout ports +2.23
How can I remove a binary from history? +3.80
Does "signal" imply δ delay in VHDL? 0.00
How to use async with lambdas which does not return anything? 0.00
Which data type in verilog is equivalent to "variable" in... 0.00
How can I browse Git Logs without Tig? -0.35
Virtually flustered with virtual ints -3.29
how to use xilinx macros in activeHDL? 0.00
QtDbus c++ minimal example +0.08
Database-like search algorithm in C++ -0.07
Homegrown workqueue vs Intel TBB -1.95
Can a C++ user-defined literal operator ever be passed a null point... 0.00
What open source C or C++ libraries can convert arbitrary UTF-32 to... 0.00
How to test a VHDL file 0.00
When will HEAD~ and HEAD^ not be the same commit? +5.03
CPPUTest debugging - C++ 0.00
VHDL 'generate' FSM states 0.00
fixed point conversion from a real variable in vhdl +0.60
Can I add a string to my commit messages before sending them to SVN... +5.15
C++ Boost Asio Simple Chat Tutorial -3.94
Reduce delay by understanding Xilinx Synthesis report +4.21
What are the advantages of boost::noncopyable -3.06
Git - Private Multi-repo ticket/issue system -4.51
Ignoring files in git cvsimport 0.00
C++0x, user-defined literals with friend operator ""() +0.38
GIT -- Exclude / Ignore Files from commit -3.77
Why does the output of this file put the comma before the text star... -2.12
Rounding integer to floating point towards 0 -3.97
C++11 lambda as member variable? +4.34
Free Language Identifier Service? 0.00
Rational numbers in Verilog -3.68
regex: boost::xpressive vs boost::regex +2.88
PyQt4 multithreading using QThread +3.94
how to run two commands in sudo? -3.23
Should I use the smallest type possible? -3.91
Program Dependence Graphs (PDG) 0.00
error correcting code over a 4 element alphabet -0.11
TAP (Test Anything Protocol) module for VHDL 0.00
software simulator to practice vhdl 0.00
User-defined literals (Extended literals) of C++11... which compile... 0.00
include floating point library in vhdl 0.00
Hidden Features of VHDL 0.00
C++ Which is faster: Stack allocation or Heap allocation 0.00
SQLite / Firebird embedded for numeric data 0.00