StackRating

An Elo-based rating system for Stack Overflow

Home | About | Stats and Analysis | Get a Badge

Rating Stats for

Kamil Rymarz

Rating
1494.51 (4,290,912th)

Reputation
378 (341,899th)

Page: 1

Title	Δ
Instantiating module name with define macro	0.00
Is it correct for using concatenation operation in verilog instanti...	0.00
Simple verilog to control MD1715 ultrasound driver	0.00
Why does following program shows error Q and D are not declared?	0.00
verilog compiler syntax error unexpected end	+4.11
Module not Defined When Simulating Using Modelsim	0.00
Execution of Generate Block	-0.38
Asynchronous reset D flipflop code syntax error	-1.96
How to synthesize hardware for SRA instruction	-4.06
Verilog HDL behavioral coding calling modules for ALU	+4.05
using regex in searching for a field using get_field_by_name	-3.27
How to initial unpacked array with another unpacked array	+4.02
Wrong result by using $sscanf in systemVerilog	0.00
Verilog Is this synthesizable read from array	0.00
RSA Python & Extended Euclidean algorithm to generate the priva...	-4.01
Using Generate Block/ Loop to Make a Ripple Carry Adder	-3.99
SystemVerilog Assertion for valid (request) - ack checking?	0.00
Convert asynchronous active low set D flip-flop to asynchronous act...	0.00
creating test bench for AXI bus	0.00