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Rating Stats for

gsm

Rating
1506.15 (120,222nd)

Reputation
352 (362,070th)

Page: 1

Title	Δ
5 seconds Timer in VHDL	0.00
VHDL Entity port does not match type of component port	0.00
Unsigned multiplication in VHDL 4bit vector?	+3.98
Pseudo Random Number Generator using LFSR in VHDL	0.00
VHDL 10 bit Shift Register	+4.02
VHDL signal assignment	-2.13
Raise a number to a power that varies in VHDL	+3.93
Better to use block RAM or distributed RAM?	-0.01
Signal is not activating process?	0.00
Frequency of the Multiplier	0.00
elaboration freezes when assigning variable x:= x + y	+4.14
Difference between assigning signal inside process vs assigning act...	+2.52
Differences between pipeline and rising_edge in vhdl?	-2.96
ISim shows U for all outputs	0.00
Synthesis global instance count	-3.17
FPGA be automatically programmed?	-4.15
VHDL syntax error when using if/then statement in a process	0.00
VHDL - if < statement not working	0.00
VHDL: why is NOT 'Z' = 'X'	0.00
when does a change in a variable in the sensitivity list trigger a...	0.00
Synth 8-2715 syntax error near	0.00