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Adhamzhon Shukurov

Rating
1507.99 (91,231st)

Reputation
417 (316,133rd)

Page: 1

Title	Δ
How to interface Red Pitaya FPGA with server code using Vivado	+0.03
Finding the maximum value of an array in log2 time in Verilog?	0.00
STM32 (using Mbed online) showing delay at higher analog input freq...	0.00
How to fix 'unknown module type error' when i run the veril...	0.00
Why are my Verilog output registers only outputting "x"?	0.00
How to assign initial value to an input reg: Design compiler delete...	0.00
Verilog expand each bit n times	-1.89
Quartus 2 - No output dependent on input / Output pins are stuck	0.00
Which part of the Android source code determines initial Android ti...	+3.66
Memorising a value from a push button	0.00
Change column into row after a given number N	+4.64
verilog synthesis not converging after 2000 iterations	+4.07
logic operations on multidimensional arrays in verilog	0.00
Can't spot the bug in my rotate matrix code	-2.51