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Khaled Ismail

Rating
1484.14 (4,476,696th) 		Reputation
114 (659,374th)
Page: 1
Title Δ
Modelsim/Questasim unit delay simulation 0.00
Verilog cannot synthesize when using external counter inside genera... -3.77
Systemverilog assertion throughout syntax +0.20
If statement in a for loop VHDL -3.84
Change directory to C or D drive using Ubuntu 18.04 LTS Windows 10... -3.98
How to reverse order of a set array -0.98
Can I convert int to string without including any libraries except... 0.00
so many error when i add certain .cpp file 0.00
Failing to make an array of Images in Python 0.00
Not getting the relevant output in my 32-bit ALU using gate-level v... -0.09
Plain text to C array test vectors -1.77
Why is fstream reading 0 from a file? +0.57
Considering a specific name for the downloaded file -4.05
How to fix "This file is not part of any project. The code mod... -2.21
How can I install the mat2vec Python package? +4.05