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In synthesizable verilog, can we use assign statement in generate block?
| Author | Votes | Δ |
|---|---|---|
| ngwilliams | 0 | +0.08 |
| Akaberto | 0 | +0.01 |
| Morgan | 0 | -0.01 |
Last visited: Sep 14, 2014, 5:07:29 AM