StackRating

An Elo-based rating system for Stack Overflow

Home | About | Stats and Analysis | Get a Badge

Rating Stats for

Morgan

Rating
1511.40 (62,220th)

Reputation
15,904 (8,804th)

Page: 1 2 3 ... 10

Title	Δ
Verilog 2's complement adder/subtraction	-0.00
Declaring the fixed-point numbers in fractional format in Verilog	0.00
Verilog accumulation code error	-0.33
Variable size and number of port/array port in module which are par...	0.00
PHP function block like in Verilog HDL	0.00
Verilog Signed Addition Subtraction error	-1.66
How do we declare wires (interconnections in a digital circuit) whe...	-0.03
displaying fractions in systemverilog	-1.75
Verilog code for Clarke and Park transformations	0.00
error in verilog : warning using System verilog 'N bit vector?	-1.80
Verilog/SystemVerilog inferred latch in case statement	-0.52
Curly braces in verilog	0.00
NOTSTT error: expecting a statement in verilog	0.00
How do I correctly use `always` blocks?	-0.03
Exponential decay in Verilog	0.00
Instanciation failing with SV code	0.00
Iteration limit when implementing a multicycled processor	0.00
how to out fixed point value in verilog?	0.00
Using reg output as input Verilog	+0.42
Condition: Logical state of multi-bit packed array	+0.07
Verilog code to compute cosx using Taylor series approximation	0.00
Maximum block of bits of 1 in a 32 bits array Verilog	-0.02
Converting this schematic to verilog code, compile unsucessful	+0.46
Accessing register depending their address	-0.03
how do I represent negative decimal verilog	0.00
verilog bit shift with 1	-0.20
What is the tip for change the value of a reg in 2 always block?	0.00
how to write case statement in verilog for 24 cases?	0.00
D-flip flop with 2 reset: synthesis error	+0.48
Designing a 3-bit counter using T-flipflop	0.00
Verilog code involving always blocks	0.00
How to create synthesizeable delay?	-0.01
How do I sign extend in SystemVerilog?	-0.62
Verilog 32-bit ALU with Overflow, Sign, and Zero Flags	0.00
Verilog display reg value based on fraction length	0.00
syntax error in verilog code ,near "<=": syntax error,...	+0.50
Ways to implement recipricals on Verilog	+0.47
Arithmetic Equation in Verilog divided by levels with clocks, recei...	0.00
nested for loops in verilog that second for loop depends upon outpu...	0.00
How to use float numbers with quartus megawizard ALTMULT_ACCUM(MAC)?	0.00
What is wrong? I can't findout the error	-0.02
In verilog Part-select of vector reg array is illegal	+0.45
Verilog Matrix multiplication error in synthesis	-1.79
How can I see real values of fixed-point numbers in waveform with M...	0.00
Verilog blocking assignment not blocking	0.00
Tasktop.v(10): (vlog-2110) Illegal reference to net "b"	-0.03
Indexed part select synthesizable in verilog	+0.48
Trying to perform addition of two fractional fixed_point operands i...	0.00
Why do Arithmetic Verilog books perform operations using Gates Logi...	-0.23
I get this error vlog-13069	0.00