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Rating Stats for

Morgan

Rating
1511.40 (62,220th)

Reputation
15,904 (8,804th)

Page: 1 2 3 4 5 ... 10

Title	Δ
$rtoi() is not a constant system function	0.00
Feedback on Mux fail to run in Verilog	0.00
feedback on mux in verilog	-0.54
verilog code to convert binary input into residue number system	0.00
Verilog: cannot be driven by primitive or continous assignment	0.00
SIGN EXTEND FROM 6 TO 16-BITS	0.00
16bit fixed point arithmetic multiplication	-0.10
Floating point numbers multiplication in verilog	0.00
Verilog: Sum over n register	+0.52
verilog code containing adders	0.00
Why two exactly "wire" statement in systemverilog, one ca...	0.00
How to make connection between wire signal of top module and inout...	+0.48
Generate Statement in verilog for multiple Blocks	0.00
Error in testbench as Inout port 'A' of 'DIGITADD'...	0.00
Mixing blocking and non-blocking assign in Verilog (or not!)	+0.52
LSFR counter for random number	+0.47
Function to calculate a value inside a Verilog generate loop	0.00
Recieving the following error: "line 36 expecting 'endmodu...	0.00
Can I make 4x4 multiplier only using 2x2 multiplier?	-0.03
What is the improve way to multiplying by 15?	+2.18
Setting Probes for SimVision in Verilog Code	+0.19
How to check signal drive strength?	0.00
how can I apply fixed fraction to the integer	0.00
What is the result of synthesis?	0.00
Multiplication by power series summation with negative terms	+0.31
Passing an array to a named port connection	0.00
How does Verilog unroll nested for loops?	0.00
System Verilog simulation versus execution	0.00
Logical and in verilog	0.00
What is the purpose ring counters?	0.00
What exactly does parallel fork join parallel?	0.00
How much have xxx precision binary fixed point representation?	0.00
Writing testbench in Modelsim	0.00
Verilog - Addition with negative numbers	0.00
Why systemverilog 4 state variables require more memory?	0.00
7 segments display LED, need some explaination	0.00
How to improve the speed of a multiplier in verilog?	0.00
Inferring latches in Verilog/SystemVerilog	0.00
How to dynamically reverse the bit position in verilog?	-0.29
variable clock generation in verilog using task	0.00
Verilog simulation error in Modelsim 10.4 SE	0.00
(Verilog) Problems assigning to LEDs in a case block	-0.02
replication operator in verilog or sv	-1.16
compare fixed point binary number with an integer	0.00
Verilog: multidimensional registered outputs	0.00
how to map memory for 16 ports in verilog	-0.02
How to pass value to `define N	0.00
Why is an always followed by assign?	0.00
Verilog - Floating points multiplication	0.00
4 bit Bi-Directional counter in verilog	0.00