StackRating
An Elo-based rating system for Stack Overflow
Answers and rating deltas for
Verilog: one clock cycle delay using register
| Author | Votes | Δ |
|---|---|---|
| Greg | 1 | +0.50 |
| Kirill Bulygin | 0 | -3.96 |
Last visited: Aug 21, 2017, 10:48:17 AM